Efforts to increase the integration density of packaged integrated circuits have frequently included the development of multi-chip modules that can be vertically integrated within single packaged substrate. Techniques to provide vertical integration have frequently included the use of solder bonds between pads and terminals of a plurality of chips that are bonded together in a vertical arrangement. One conventional technique to provide vertical integration is disclosed in US 2002/0109236 to Kim et al., entitled “Three-Dimensional Multi-Chip Package Having Chip Selection Pads and Manufacturing Method Thereof.” Another conventional technique is disclosed in US 2005/0233581 to Soejima et al., entitled “Method for Manufacturing Semiconductor Device.” Still further techniques are disclosed in US 2007/0001312 to Murayama et al., entitled “Semiconductor Chip and Method of Manufacturing the Same.”